Please refer to FIG. 1, which is a functional block diagram schematically showing a typical digital data writing-in and reading-out system. As shown, the reference label “u” indicates a digital data sequence. A written-in signal X suitable to be recorded by a digital data recording medium is generated after the digital data sequence u is encoded by a run-length limited and non-return to zero encoder (hereinafter, RLL-NRZ encoder) 11. The written-in signal X is then written into the digital data recording medium 10 by a writing-in device 12. Afterwards, the signal stored in the digital data recording medium 10 can be read out via a pickup head 13, which is further transmitted via a channel and adjusted by an equalizer 14 into a signal Y. The signal Y is then decoded by a Viterbi decoder 15 to be transformed into a read-out signal X′ having the same format as the written-in signal X. Then, a recovered digital data sequence u′ is obtained by decoding the read-out signal X′ with a run-length limited and non-return to zero decoder (hereinafter, RLL-NRZ decoder) 16.
The above digital data writing-in and reading-out system is generally used in a disk drive system or an optical disk drive system. Giving an optical disk drive system as an example, the equalizer 14, Viterbi decoder 15 and RLL-NRZ decoder 16 can be arranged in a control chip of the optical disk drive.
Further referring to FIG. 2, the transformation of the written-in signal X into the signal Y is illustrated. The written-in signal X, for example, consists of levels +0.5 and −0.5. Before the written-in signal X is transformed into the signal Y by the equalizer 14, it is processed into a signal Z first via a channel 20. The channel 20 substantially involves all factors that the written-in signal X encounters after it is read out from the digital data recording medium 10 and before it enters the equalizer 14. The transfer function of the channel 20 is defined as “Z(D)/X(D)=1+a1*D+a2* D^2+a3*D^3+a4+ . . . ”. On the other hand, the channel 20 and the equalizer 14 can be combined as a partial response (PR) channel with an input signal X and an output signal Y. Accordingly, the transfer function can be adjusted into “Y(D)/X(D)=PR(1,1)=1+D”, “Y(D)/X(D)=PR (1,2, 1)=1+2*D+D{circumflex over (0 )}2” or “Y(D)/X(D)=PR(1,1,1,1)=1+D+D{circumflex over (0 )}2+D{circumflex over (0 )}3”. Table 1 lists the relationship between the transfer functions and their corresponding target levels, i.e. the ideal levels of the signal Y.
TABLE 1Transfer function Y(D)/X(D)Target levelsPR(1,1) = 1 + D−1, 0, 1PR(1,2,1) = 1 + 2*D + D 2−2, −1, 1, 2PR(1,1,1,1) = 1 + D + D 2 +−2, −1, 0, 1, 2D 3
As is understood by those skilled in the art, the Viterbi decoder 15, which transforms the signal Y into the read-out signal X′ having the same format as the written-in data X according to a Viterbi algorithm, involves the storage and operation of a large quantity of data. For enhancing the data-processing rate of the digital data writing-in and reading-out system, two Viterbi decoders are provided, as shown in FIG. 3. A first Viterbi decoder 151 and a second Viterbi decoder 152 are used to process the odd signal Y1 and even signal Y2 of the data sequence into two read-out signals X1′ and X2′, respectively. Since a Viterbi decoder has complicated circuitry, two Viterbi decoders will occupy large area of the control chip and increase cost.